CSDL sách
- Logic-timing simulation and the degradation delay model
- Tác giả: Manuel Jesus Bellido Diaz, Jorge Juan Chico, Manuel Valencia
- Nhà xuất bản: Imperial College Press - London
- Năm xuất bản: 2006
- Số trang:264 p.
- Kích thước:24 cm
- Số đăng ký cá biệt:48269
- ISBN:9781860945892
- Mã Dewey:003.3
- Đơn giá:0
- Vị trí lưu trữ:03 Quang Trung
- Ngôn ngữ:English
- Loại tài liệu:Sách Tham Khảo
- Đang rỗi/ Tổng sách:4/4
- Từ khóa:Computer simulation, mathematical models, timing circuits
- Chủ đề: Mathematical models & Computer simulation
- Chuyên ngành: Khoa Công Nghệ Thông Tin
- Tóm tắt: This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the "Degradation Delay Model", developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the application cases and accuracy of logic-timing simulation. These ideas are supported by simulation results extracted from a wide range of practical applications.Sample Chapter(s).
- Sách điện tử:http://thuvienso.duytan.edu.vn/handle/123456789/294428
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