CSDL sách
- Verilog by example : a concise introduction for FPGA design
- Tác giả: Blaine C. Readler
- Nhà xuất bản: Full Arc Press - United States of America
- Năm xuất bản: 2019
- Số trang:114 p.
- Kích thước:23 cm
- Số đăng ký cá biệt:45059
- ISBN:9780983497301
- Mã Dewey:621.392
- Đơn giá:0
- Vị trí lưu trữ:03 Quang Trung
- Ngôn ngữ:English
- Loại tài liệu:Sách Chuyên ngành
- Đang rỗi/ Tổng sách:1/1
- Từ khóa:Field programmable gate arrays, Verilog, Computer hardware description language
- Chủ đề: Field programmable gate arrays & Verilog
- Chuyên ngành: Khoa Điện - Điện tử
- Tóm tắt: Starting with a simple but workable design sample, increasingly more complex fundamentals of the language are introduced until all major features of verilog are brought to light. Included in the coverage are state machines, modular design, FPGA-based memories, clock management, specialized I/O, and an introduction to techniques of simulation. The goal is to prepare the reader to design real-world FPGA solutions. All the sample code used in the book is available online. What Strunk and White did for the English language with "The Elements of Style," verilog by example does for FPGA design.
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