CSDL SÁCH
Metal oxide semiconductors
Duyệt theo:
Logical effort: Designing fast CMOS circuits
The method of logical effort, design examples, deriving the method of logical effort, calculating the logical effort of gates, calibrating the model, asymmetric logic gates, unequal rising and falling delays, circuit families, forks of amplifiers, branches and interconnect, ...
- Vị trí lưu trữ: Tồn kho (03 Quang Trung)
- Tổng sách: 1
- Đang rỗi: 1